Nanowires are a viable device option for continuing complementary metal-oxide semiconductor (CMOS) scaling. Stacked nanowires provide area efficiency, i.e., increasing drive current at a given layout area.
One drawback to the stacked nanowire design is that the minimum device width is the periphery of each of one nanowire stack. However, it is desired in some applications to have the flexibility to adjust the effective device width beyond the integral number of nanowire stacks. For instance, one example is static random access memory (SRAM) in which the ratio of n-channel field effect transistor (NFET) and p-channel FET (PFET) device widths may be a decimal, say 1.5 instead of 1 or 2. Such a device configuration cannot be achieved using current processing technology.
Therefore, there is a need for forming stacked nanowire devices with tunable effective device width.